In a typical computer system, multiple devices are able to write data to and read data from a main memory. A memory controller couples these devices with the main memory and controls the timing and sequence of such data transfer operations. Referring to FIG. 1, a memory controller 10 includes arbiter circuitry 12 that receives a plurality of signals indicative of requests for data transfer operations-commonly known as priority requests PREQ .0.-PREQ M. Each of these priority request signals corresponds to a device requesting to write data to or read data from a main memory 14. Example devices include a microprocessor and input/output (I/O) devices, such as peripheral component interconnect (PCI) bus devices, industry standard architecture (ISA) bus devices, integrated drive electronics (IDE) devices, accelerated graphics port (AGP) devices, small computer system interface (SCSI) devices, and universal serial bus (USB) devices, to name just a few examples. The arbiter 12 prioritizes the various priority requests, and the memory controller 10 correspondingly initiates and controls the data transfer operations.
Typically, the priority requests are simply queued by the arbiter 12, with the requested data transfer operations occurring on a first-come first-served basis. Certain of today's computer systems can reorder some data transfer operations, such as by providing "read around write" capability. Also, certain computer systems allow various write operations to be reordered or combined to minimize the frequency of write operations to the memory subsystem. Some computer systems provide fixed service priorities, in which priority requests from some devices (e.g., the CPU) always receive service prior to priority requests from other devices.
Many devices included in today's computer systems have maximum latency requirements--i.e., a maximum time interval following the requested data transfer operation by which such operation must be effected. For example, a video display device typically requires regular refresh of the display. The display refresh must occur regularly and timely to avoid undesirable artifacts showing on the display. As another example, a software-based modem requires timely transfer of coder/decoder (CODEC) data in order to avoid corruption of the modem data. To satisfy such latency requirements, today's computer systems include separately dedicated memories or device buffers. For example, the video display in today's computer systems commonly has a separately dedicated video memory and associated video memory controller. As another example, software-based modems have a large CODEC data buffers for storing received data and transmit data.
Given the improved production economies and performance improvements offered by today's increasingly integrated computer systems, it is highly desirable to minimize the number of separately dedicated memory circuits and associated controller circuits. However, today's main memory access arbitration schemes cannot satisfy the latency requirements of certain devices commonly included in a computer system.